conf/dts/ac7020c-sdt/cortexa9-linux.dts
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-7000";
model = "Xilinx Zynq";
device_id = "7z020";
slrcount = <0x1>;
family = "Zynq";
speed_grade = "2";
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x3000000>;
};
};
cpus_a9: cpus {
phandle = <0x30>;
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "cpus,cluster";
#ranges-address-cells = <0x1>;
#ranges-size-cells = <0x1>;
ps7_cortexa9_0: cpu@0 {
phandle = <0x2c>;
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <&clkc 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <®ulator_vccpint>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <0x14>;
xlnx,i-cache-line-size = <0x14>;
xlnx,cpu-1x-clk-freq-hz = <0x69f6bcb>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,d-cache-size = <0x8000>;
xlnx,num-cores = <0x2>;
xlnx,cpu-clk-freq-hz = <0x27bc86bf>;
bus-handle = <0x1>;
};
ps7_cortexa9_1: cpu@1 {
phandle = <0x2e>;
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <&clkc 0x3>;
xlnx,i-cache-size = <0x8000>;
xlnx,d-cache-line-size = <0x14>;
xlnx,i-cache-line-size = <0x14>;
xlnx,cpu-1x-clk-freq-hz = <0x69f6bcb>;
xlnx,ip-name = "ps7_cortexa9";
xlnx,d-cache-size = <0x8000>;
xlnx,cpu-clk-freq-hz = <0x27bc86bf>;
bus-handle = <0x1>;
};
};
fpga_full: fpga-region {
phandle = <0x31>;
compatible = "fpga-region";
fpga-mgr = <&devcfg>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu@f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <&intc>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
regulator_vccpint: fixedregulator {
phandle = <0x23>;
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
};
replicator {
compatible = "arm,coresight-static-replicator";
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
out-ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
replicator_out_port0: endpoint {
phandle = <0x28>;
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <0x1>;
replicator_out_port1: endpoint {
phandle = <0x27>;
remote-endpoint = <&etb_in_port>;
};
};
};
in-ports {
port {
replicator_in_port0: endpoint {
phandle = <0x29>;
remote-endpoint = <&funnel_out_port>;
};
};
};
};
amba: axi {
phandle = <0x1>;
bootph-all;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <&intc>;
ranges;
adc: adc@f8007100 {
phandle = <0x21>;
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <&intc>;
clocks = <&clkc 0xc>;
status = "okay";
xlnx,ip-name = "ps7_xadc";
};
can0: can@e0008000 {
phandle = <0x32>;
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 0x13>,
<&clkc 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
phandle = <0x33>;
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 0x14>,
<&clkc 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
phandle = <0x11>;
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <&clkc 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
xlnx,mio-gpio-mask = <0x5600>;
status = "okay";
gpio-mask-high = <0x0>;
xlnx,emio-gpio-width = <0x4>;
xlnx,ip-name = "ps7_gpio";
gpio-mask-low = <0x5600>;
emio-gpio-width = <0x4>;
};
i2c0: i2c@e0004000 {
phandle = <0x34>;
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 0x26>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x19 0x4>;
clock-frequency = <0x61a80>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c1: i2c@e0005000 {
phandle = <0x35>;
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 0x27>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x30 0x4>;
clock-frequency = <0x61a80>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
intc: interrupt-controller@f8f01000 {
phandle = <0x13>;
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
status = "okay";
xlnx,irq-f2p-mode = "DIRECT";
xlnx,ip-name = "ps7_intc_dist";
};
L2: cache-controller@f8f02000 {
phandle = <0x15>;
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
status = "okay";
xlnx,ip-name = "ps7_pl310";
};
mc: memory-controller@f8006000 {
phandle = <0xb>;
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
status = "okay";
xlnx,ddr-clk-freq-hz = <0x1fca057e>;
xlnx,ip-name = "ps7_ddrc";
xlnx,has-ecc = <0x0>;
};
ocm: sram@fffc0000 {
phandle = <0x36>;
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0x0 0xfffc0000 0x10000>;
ocm-sram@0 {
reg = <0x0 0x10000>;
};
};
uart0: serial@e0000000 {
phandle = <0x37>;
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 0x17>,
<&clkc 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
interrupt-parent = <&intc>;
};
uart1: serial@e0001000 {
phandle = <0x20>;
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <&clkc 0x18>,
<&clkc 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
interrupt-parent = <&intc>;
device_type = "serial";
xlnx,clock-freq = <0x5f5e100>;
xlnx,has-modem = <0x0>;
xlnx,ip-name = "ps7_uart";
cts-override;
port-number = <0x0>;
xlnx,uart-clk-freq-hz = <0x5f5e100>;
};
spi0: spi@e0006000 {
phandle = <0x38>;
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0x0 0x1a 0x4>;
clocks = <&clkc 0x19>,
<&clkc 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi1: spi@e0007000 {
phandle = <0x1f>;
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "okay";
interrupt-parent = <&intc>;
interrupts = <0x0 0x31 0x4>;
clocks = <&clkc 0x1a>,
<&clkc 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
xlnx,has-ss0 = <0x1>;
xlnx,ip-name = "ps7_spi";
xlnx,has-ss1 = <0x0>;
num-cs = <0x4>;
xlnx,spi-clk-freq-hz = <0x9ef21b0>;
xlnx,has-ss2 = <0x0>;
cs-gpios = <0x11 0x36 0x1 0x11 0x37 0x1 0x11 0x38 0x1 0x11 0x39 0x1>;
pot0: spidev@0 {
phandle = <0x3>;
compatible = "rohm,dh2228fv";
reg = <0x0>;
spi-max-frequency = <0x989680>;
};
pot1: spidev@1 {
phandle = <0x4>;
compatible = "rohm,dh2228fv";
reg = <0x1>;
spi-max-frequency = <0x989680>;
};
pot2: spidev@2 {
phandle = <0x6>;
compatible = "rohm,dh2228fv";
reg = <0x2>;
spi-max-frequency = <0x989680>;
};
pot3: spidev@3 {
phandle = <0x7>;
compatible = "rohm,dh2228fv";
reg = <0x3>;
spi-max-frequency = <0x989680>;
};
};
qspi: spi@e000d000 {
phandle = <0x18>;
compatible = "xlnx,zynq-qspi-1.0";
reg = <0xe000d000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x13 0x4>;
clocks = <&clkc 0xa>,
<&clkc 0x2b>;
clock-names = "ref_clk", "pclk";
status = "okay";
#address-cells = <0x1>;
#size-cells = <0x0>;
xlnx,qspi-fbclk = <0x0>;
num-cs = <0x1>;
xlnx,qspi-clk-freq-hz = <0xbebc200>;
xlnx,bus-width = <0x2>;
xlnx,ip-name = "ps7_qspi";
spi-rx-bus-width = <0x4>;
xlnx,connection-mode = <0x0>;
spi-tx-bus-width = <0x4>;
xlnx,clock-freq = <0xbebc200>;
xlnx,fb-clk = <0x0>;
xlnx,qspi-mode = <0x0>;
xlnx,qspi-bus-width = <0x2>;
is-dual = <0x0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <0x2faf080>;
#address-cells = <0x1>;
#size-cells = <0x1>;
partition@0 {
label = "qspi-boot";
reg = <0x0 0x500000>;
};
partition@1 {
label = "qspi-bootenv";
reg = <0x500000 0x20000>;
};
partition@2 {
label = "qspi-kernel";
reg = <0x520000 0x1a80000>;
};
};
};
gem0: ethernet@e000b000 {
phandle = <0xf>;
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
interrupt-parent = <&intc>;
clocks = <&clkc 0x1e>,
<&clkc 0x1e>,
<&clkc 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
xlnx,has-mdio = <0x1>;
phy-mode = "rgmii-id";
xlnx,enet-slcr-1000mbps-div0 = <0x8>;
xlnx,enet-slcr-10mbps-div0 = <0x8>;
xlnx,enet-slcr-1000mbps-div1 = <0x1>;
xlnx,enet-slcr-10mbps-div1 = <0x32>;
xlnx,ip-name = "ps7_ethernet";
xlnx,eth-mode = <0x1>;
xlnx,enet-clk-freq-hz = <0x7735940>;
xlnx,enet-slcr-100mbps-div0 = <0x8>;
xlnx,ptp-enet-clock = <0x69f6bcb>;
xlnx,enet-slcr-100mbps-div1 = <0x5>;
};
gem1: ethernet@e000c000 {
phandle = <0x39>;
compatible = "xlnx,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
interrupt-parent = <&intc>;
clocks = <&clkc 0x1f>,
<&clkc 0x1f>,
<&clkc 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
smcc: memory-controller@e000e000 {
phandle = <0x3a>;
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x1000>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 0xb>,
<&clkc 0x2c>;
ranges = <0x0 0x0 0xe1000000 0x1000000 0x1 0x0 0xe2000000 0x2000000 0x2 0x0 0xe4000000 0x2000000>;
#address-cells = <0x2>;
#size-cells = <0x1>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x12 0x4>;
nfc0: nand-controller@0,0 {
phandle = <0x3b>;
compatible = "arm,pl353-nand-r2p1";
reg = <0x0 0x0 0x1000000>;
status = "disabled";
};
nor0: flash@1,0 {
phandle = <0x3c>;
status = "disabled";
compatible = "cfi-flash";
reg = <0x1 0x0 0x2000000>;
};
};
sdhci0: mmc@e0100000 {
phandle = <0x1d>;
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 0x15>,
<&clkc 0x20>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
xlnx,has-power = <0x0>;
xlnx,ip-name = "ps7_sdio";
xlnx,sdio-clk-freq-hz = <0x5f5e100>;
xlnx,has-wp = <0x0>;
xlnx,has-cd = <0x0>;
};
sdhci1: mmc@e0101000 {
phandle = <0x3d>;
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 0x16>,
<&clkc 0x21>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr: slcr@f8000000 {
phandle = <0x1e>;
bootph-all;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
status = "okay";
xlnx,ip-name = "ps7_slcr";
clkc: clkc@100 {
phandle = <0x22>;
bootph-all;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0x1>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
};
rstc: rstc@200 {
phandle = <0x3e>;
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
phandle = <0x3f>;
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
};
};
dmac_s: dma-controller@f8003000 {
phandle = <0xe>;
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
clocks = <&clkc 0x1b>;
clock-names = "apb_pclk";
status = "okay";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
};
devcfg: devcfg@f8007000 {
phandle = <0xc>;
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x8 0x4>;
clocks = <&clkc 0xc>,
<&clkc 0xf>,
<&clkc 0x10>,
<&clkc 0x11>,
<&clkc 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
status = "okay";
xlnx,ip-name = "ps7_dev_cfg";
};
efuse: efuse@f800d000 {
phandle = <0x40>;
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
global_timer: timer@f8f00200 {
phandle = <0x10>;
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <&intc>;
clocks = <&clkc 0x4>;
status = "okay";
xlnx,ip-name = "ps7_globaltimer";
};
ttc0: timer@f8001000 {
phandle = <0x41>;
interrupt-parent = <&intc>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <&clkc 0x6>;
reg = <0xf8001000 0x1000>;
};
ttc1: timer@f8002000 {
phandle = <0x42>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <&clkc 0x6>;
reg = <0xf8002000 0x1000>;
};
scutimer: timer@f8f00600 {
phandle = <0x1b>;
bootph-all;
interrupt-parent = <&intc>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <&clkc 0x4>;
status = "okay";
xlnx,ip-name = "ps7_scutimer";
};
scuwdt: scuwatchdog@f8f00620 {
phandle = <0x1c>;
interrupt-parent = <&intc>;
interrupts = <0x1 0xe 0x4>;
compatible = "xlnx,ps7-scuwdt-1.00.a";
reg = <0xf8f00620 0xe0>;
status = "okay";
xlnx,ip-name = "ps7_scuwdt";
};
usb0: usb@e0002000 {
phandle = <0x43>;
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 0x1c>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
};
usb1: usb@e0003000 {
phandle = <0x44>;
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 0x1d>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog0: watchdog@f8005000 {
phandle = <0x45>;
clocks = <&clkc 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <&intc>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
coresight: coresight@f8800000 {
phandle = <0xa>;
compatible = "xlnx,ps7-coresight-comp-1.00.a";
status = "okay";
reg = <0xf8800000 0x100000>;
xlnx,ip-name = "ps7_coresight_comp";
};
etb@f8801000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0xf8801000 0x1000>;
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
etb_in_port: endpoint {
phandle = <0x25>;
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
tpiu@f8803000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0xf8803000 0x1000>;
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
in-ports {
port {
tpiu_in_port: endpoint {
phandle = <0x24>;
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
funnel@f8804000 {
compatible = "arm,coresight-static-funnel", "arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
out-ports {
port {
funnel_out_port: endpoint {
phandle = <0x26>;
remote-endpoint = <&replicator_in_port0>;
};
};
};
in-ports {
#address-cells = <0x1>;
#size-cells = <0x0>;
port@0 {
reg = <0x0>;
funnel0_in_port0: endpoint {
phandle = <0x2d>;
remote-endpoint = <&ptm0_out_port>;
};
};
port@1 {
reg = <0x1>;
funnel0_in_port1: endpoint {
phandle = <0x2f>;
remote-endpoint = <&ptm1_out_port>;
};
};
port@2 {
reg = <0x2>;
};
};
};
ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_0>;
out-ports {
port {
ptm0_out_port: endpoint {
phandle = <0x2a>;
remote-endpoint = <&funnel0_in_port0>;
};
};
};
};
ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = <&clkc 0x1b>,
<&clkc 0x2e>,
<&clkc 0x2f>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
cpu = <&ps7_cortexa9_1>;
out-ports {
port {
ptm1_out_port: endpoint {
phandle = <0x2b>;
remote-endpoint = <&funnel0_in_port1>;
};
};
};
};
ps7_dma_ns: ps7_dma@f8004000 {
phandle = <0xd>;
compatible = "xlnx,ps7-dma-1.00.a";
status = "okay";
xlnx,ip-name = "ps7_dma";
xlnx,is-secure;
reg = <0xf8004000 0x1000>;
};
ps7_qspi_linear_0: ps7_qspi_linear@fc000000 {
phandle = <0x4a>;
reg = <0xfc000000 0x1000000>;
};
};
amba_pl: amba_pl {
phandle = <0x4b>;
ranges;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
firmware-name = "ac7020c_wrapper.bit.bin";
timing_controller_0: timing_controller@43c00000 {
phandle = <0x5>;
xlnx,s00-axi-data-width = <0x20>;
compatible = "generic-uio", "uio";
status = "okay";
clock-names = "s00_axi_aclk";
xlnx,s00-axi-addr-width = <0x9>;
xlnx,ip-name = "timing_controller";
xlnx,edk-iptype = "PERIPHERAL";
reg = <0x43c00000 0x200>;
clocks = <&clkc 0xf>;
};
};
ps7_ddr_0_memory: memory@0 {
phandle = <0x2>;
xlnx,ip-name = "ps7_ddr";
device_type = "memory";
memory_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = "/axi/serial@e0001000";
spi0 = "/axi/spi@e000d000";
serial1 = "/axi/coresight@f8800000";
ethernet0 = "/axi/ethernet@e000b000";
};
__symbols__ {
cpus_a9 = "/cpus-a9@0";
ps7_cortexa9_0 = "/cpus-a9@0/cpu@0";
ps7_cortexa9_1 = "/cpus-a9@0/cpu@1";
fpga_full = "/fpga-region";
regulator_vccpint = "/fixedregulator";
replicator_out_port0 = "/replicator/out-ports/port@0/endpoint";
replicator_out_port1 = "/replicator/out-ports/port@1/endpoint";
replicator_in_port0 = "/replicator/in-ports/port/endpoint";
amba = "/axi";
adc = "/axi/adc@f8007100";
can0 = "/axi/can@e0008000";
can1 = "/axi/can@e0009000";
gpio0 = "/axi/gpio@e000a000";
i2c0 = "/axi/i2c@e0004000";
i2c1 = "/axi/i2c@e0005000";
intc = "/axi/interrupt-controller@f8f01000";
L2 = "/axi/cache-controller@f8f02000";
mc = "/axi/memory-controller@f8006000";
ocm = "/axi/sram@fffc0000";
uart0 = "/axi/serial@e0000000";
uart1 = "/axi/serial@e0001000";
spi0 = "/axi/spi@e0006000";
spi1 = "/axi/spi@e0007000";
qspi = "/axi/spi@e000d000";
gem0 = "/axi/ethernet@e000b000";
gem1 = "/axi/ethernet@e000c000";
smcc = "/axi/memory-controller@e000e000";
nfc0 = "/axi/memory-controller@e000e000/nand-controller@0,0";
nor0 = "/axi/memory-controller@e000e000/flash@1,0";
sdhci0 = "/axi/mmc@e0100000";
sdhci1 = "/axi/mmc@e0101000";
slcr = "/axi/slcr@f8000000";
clkc = "/axi/slcr@f8000000/clkc@100";
rstc = "/axi/slcr@f8000000/rstc@200";
pinctrl0 = "/axi/slcr@f8000000/pinctrl@700";
dmac_s = "/axi/dma-controller@f8003000";
devcfg = "/axi/devcfg@f8007000";
efuse = "/axi/efuse@f800d000";
global_timer = "/axi/timer@f8f00200";
ttc0 = "/axi/timer@f8001000";
ttc1 = "/axi/timer@f8002000";
scutimer = "/axi/timer@f8f00600";
scuwdt = "/axi/scuwatchdog@f8f00620";
usb0 = "/axi/usb@e0002000";
usb1 = "/axi/usb@e0003000";
watchdog0 = "/axi/watchdog@f8005000";
coresight = "/axi/coresight@f8800000";
etb_in_port = "/axi/etb@f8801000/in-ports/port/endpoint";
tpiu_in_port = "/axi/tpiu@f8803000/in-ports/port/endpoint";
funnel_out_port = "/axi/funnel@f8804000/out-ports/port/endpoint";
funnel0_in_port0 = "/axi/funnel@f8804000/in-ports/port@0/endpoint";
funnel0_in_port1 = "/axi/funnel@f8804000/in-ports/port@1/endpoint";
ptm0_out_port = "/axi/ptm@f889c000/out-ports/port/endpoint";
ptm1_out_port = "/axi/ptm@f889d000/out-ports/port/endpoint";
ps7_dma_ns = "/axi/ps7_dma@f8004000";
ps7_qspi_linear_0 = "/axi/ps7_qspi_linear@fc000000";
amba_pl = "/amba_pl";
timing_controller_0 = "/amba_pl/timing_controller@43c00000";
ps7_ddr_0_memory = "/memory@00100000";
pot0 = "/axi/spi@e0007000/spidev@0";
pot1 = "/axi/spi@e0007000/spidev@1";
pot2 = "/axi/spi@e0007000/spidev@2";
pot3 = "/axi/spi@e0007000/spidev@3";
clocking0 = "/clocking0";
};
domains {
APU_Linux {
compatible = "openamp,domain-v1";
cpus = <&cpus_a9 0x3 0x80000003>;
os,type = "linux";
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
};
};
clocking0: clocking0 {
phandle = <0x4c>;
compatible = "xlnx,fclk";
assigned-clocks = <&clkc 0xf>;
assigned-clock-rates = <0x5f5e100>;
#clock-cells = <0x0>;
clock-output-names = "fabric_clk";
clocks = <&clkc 0xf>;
};
};